商品簡介
Engineers tend to focus on logic design when developing Field Programmable Gate Arrays (FPGAs). They write good code using a Hardware Description Language (HDL) that matches an agreed-upon set of requirements. Using a Hardware Verification Language (HVL), an independent verification team ensures that the HDL code matches these requirements. Throughout the process, a suitable source control system ensures the integrity of the design and verification code. The logic design is complete.
When these tasks are complete, there is a perception that the designer can press the button in the manufacturer's design software, wait a couple of hours, download the result to the target system, and everything works. If the physical characteristics of the FPGA and the surrounding system are not considered, the design rarely works on the first try.
In FPGA design, constraints are contained in additional source files that inform the synthesis and place and route (implementation) tools on optimally creating a working FPGA using the selected device's physical properties and the physical properties of the surrounding system into account. It is important to note that the constraint file is a source file that is at least as necessary as any of the HDL files that define the logic of the system.
With FPGAs, you buy "the box" when you select the component. To be successful, you need to know how to make trade-offs between the Temporal Constraints and Spatial Constraints of "the box". The task of creating a successful FPGA design ends up being the optimization of multiple components of the system.
This text contains eight chapters. Chapter 0 describes the steps to develop good code to describe the FPGA logic. It is expected that those steps are completed before entering into the physical design phase. Chapter 1 and Chapter 2 describe Temporal Constraints and Spatial Constraints, respectively. These two chapters are the primary focus of the book. Chapter 4 describes steps used in the physical design process to achieve a successful FPGA design by optimizing the constraints and the original HDL if necessary, Chapter 5 describes good hardware design practice for FPGA Design. A description of how to stage the FPGA toolchain is shown in Chapter 6. To put things in context, Chapter 3 and Chapter 7 are case studies of how applying good design practice can lead to a successful FPGA design.
您曾經瀏覽過的商品
購物須知
外文書商品之書封，為出版社提供之樣本。實際出貨商品，以出版社所提供之現有版本為主。部份書籍，因出版社供應狀況特殊，匯率將依實際狀況做調整。
無庫存之商品，在您完成訂單程序之後，將以空運的方式為你下單調貨。為了縮短等待的時間，建議您將外文書與其他商品分開下單，以獲得最快的取貨速度，平均調貨時間為1~2個月。
為了保護您的權益，「三民網路書店」提供會員七日商品鑑賞期(收到商品為起始日)。
若要辦理退貨，請在商品鑑賞期內寄回，且商品必須是全新狀態與完整包裝(商品、附件、發票、隨貨贈品等)否則恕不接受退貨。